LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;

entity ControladorDisplay7seg is
  port(bcd3,bcd2,bcd1,bcd0 : in std_logic_vector (3 downto 0);
  ck  : in std_logic;
  displayNumerico: out std_logic_vector(7 downto 0);
  selector: out std_logic_vector(3 downto 0)
  );
end;

architecture aControladorDisplay7seg of ControladorDisplay7seg is
  component Multiplexor16a4 is
  port(
  vector3, vector2, vector1, vector0: in std_logic_vector( 3 downto 0);
  control1, control0 : in std_logic;
  salida : out std_logic_vector (3 downto 0)
  );     
  end component;
  component contador2std_logic is
  port(
	 rst : in std_logic;
	 ck: in std_logic;
	 e: in std_logic;
	 q1 : out std_logic;
	 q0 : out std_logic);
  end component;
  
  component BCDA7Segmentos is
  PORT (D:IN std_logic_vector(3 DOWNTO 0);
  O:OUT std_logic_vector(7 DOWNTO 0));
  end component;
  
  signal e_s,control1_s,control0_s: std_logic;
  signal bcd: std_logic_vector (3 downto 0); 
  
begin
  process (ck)
    variable contadorGeneradorDeEnable : natural := 0;
  begin
    if ck'event and ck='1' then
        contadorGeneradorDeEnable := contadorGeneradorDeEnable+1 ;
        if contadorGeneradorDeEnable=50000 then
          contadorGeneradorDeEnable:= 0;
          e_s<='1';
        else
          e_s<='0';  
        end if;
    end if;
  end process; 
  process (control1_s,control0_s)
  begin
    if control0_s ='0' and control1_s ='0'then
      selector <=  "1110";
  elsif control0_s ='1' and control1_s ='0'then
      selector <=  "1101";
  elsif control0_s ='0' and control1_s ='1'then
      selector <=  "1011";
  elsif control0_s ='1' and control1_s ='1'then
      selector <=  "0111";
    end if ;
  end process ;

  
  
 multiplexor: Multiplexor16a4 port map(bcd3,bcd2,bcd1,bcd0,control1_s,control0_s,bcd); 
 contador: Contador2std_logic port map ('0',ck,e_s,control1_s,control0_s); 
 bcda7 : BCDA7Segmentos port map (bcd, displayNumerico ); 
  
end;
